The present invention relates to a substrate potential generating circuit in a semiconductor integrated circuit which employs MOS IGFETs (metal-oxide-semiconductor insulated-gate field-effect transistors).
In an integrated circuit using MOS transistors, especially in a dynamic RAM (random access memory), bias is generally applied to the semiconductor substrate in order to speed up the operation of the circuit. In general, this bias is a voltage generated by a substrate potential generating circuit provided on the chip.
A conventional substrate potential generating circuit of this type is shown in FIG. 1. In this figure, reference numeral 1 designates a pulse generating circuit using a ring oscillator; 2, a power source terminal for the pulse generating circuit; 3, the output terminal of the pulse generating circuit 1; 4, a coupling capacitor; 5, a node; and 6, a rectifying MOS transistor connected between the mode 5 and ground. The gate electrode of the MOS transistor 6 is connected to the node 5, and the node side serves as an anode. Further in FIG. 1, reference numeral 7 designates a rectifying MOS transistor connected between the node 5 and a substrate potentail generating terminal (output terminal) 9. The gate electrode of the transistor 7 is connected to the output terminal 9, and the output terminal side serves as an anode. The output terminal 9 is grounded through a capcitor 8 used to stabilize the substrate potential. The above-described circuit elements 4 through 7 form the substrate potential generating circuit.
The operation of the circuit of FIG. 1 will be described with reference to the waveform diagram of FIG. 2.
The power source terminal 2 of the pulse generating circuit 1 is connected to the power source terminal of the integrated circuit. Therfore, when a supply voltage V.sub.cc is applied to the integrated circuit, the voltage V.sub.2 at the terminal 2 is increased to the value V.sub.cc immediately; however, the voltage V.sub.9 at the output terminal 9 reaches a final level V.sub.SUB only after a delay time (t.sub.0 -t.sub.1). For practical use, it has been required that the delay time is set to 100 microseconds or less in most cases.
In order to meet this requirement, the manufacturer determines parameters for the various elements as follows:
In order to generate a substrate bias, a pulse having an amplitude V.sub.cc is applied to one terminal of the coupling capacitor, or the output terminal 3 of the pulse generating circuit 1, so that a bias current is caused to flow through the coupling capacitor 4. The capacitor 8 connected to the output terminal 9 is gradually charged by this current. The final level V.sub.SUB of the voltage provided at the output terminal 9 can be represented by the following equation which is well known in the art: EQU V.sub.SUB =-(V.sub.cc -2V.sub.TH), (1)
where V.sub.TH is the threshold of each of the MOS transistor 8 is: EQU Q.sub.8 =-(V.sub.cc -2V.sub.TH)C.sub.8, (2)
where C.sub.8 is the stabilizing capacitance.
In many cases, V.sub.cc =5 V, V.sub.TH =0.5 V, and C.sub.8 =1000 Pf. Therefore, EQU Q.sub.8 -(5-1.0)1000=-4000(pQ).
Hence, the substrate bias current required for storing the above-described charge in the capacitor in 100 microseconds is: EQU I=4000pQ/100 microseconds=40 microamperes. (3)
That is, the frequency of the pulse generating circuit 1 and the capacitance of the coupling capacitor 4 are determined so that the pulse generating curcuit 1 supplies a current of 40 microamperes through the coupling capacitor to the capacitor 8.
The above-described substrate bias current is necessary in order to stabilize the substrate potential within a predetermined period of time after the application of the supply voltage V.sub.cc. In addition, the substrate bias current serves to compensate for an impact ionization current which, when the integrated circuit performs a reading or writing operation after the substrate potential has been stabilized, is caused by holes near the drain of the MOS transistor. On the other hand, when the integrated circuit is not in operation, that is, when it is in the standby state, only the reverse leakage current at the P-N junction flows. This current is, in general, on the order of several 10s of picoamperes to about 100 picoamperes. Therefore, it is unnecessary to supply a current as large as 40 microamperes.
A large number of dynamic RAMs are usually employed in a memory system. However, only a fraction of them are in operation at any one time, the remaining dynamic RAMs being in the standby state. This means that the substrate bias current is used uneconomically.